Responsibilities Develop test plans using established methodologies targeted on chip IP functions and features. Design and implement test circuits using FPGA fabric and embedded IP using Lattices proprietary design SW. Develop scripts to automate test generation and own Pre-Si verification of content to ensure Si readiness. Execute Post-Si pattern validation using wafer-level ATE, package-level ATE, and package-level bench platforms across process, temperature, and voltage conditions. Identify and analyze to root cause product marginalities, communicating and coordinating root cause closure to appropriate cross-functional team (eg. Applications Engineering, Design Engineering, etc.) Take ownership of IP content development and drive any issues to resolution. Plan and execute test content delivery to meet or exceed schedules required for internal and external customers samples. Extract coverage metrics of test patterns using fault grading and review for coverage improvements.
Lattice Overview There is energy hereenergy you can feel crackling at any of our international locations. Its an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a team first organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what youre looking for. Responsibilities & Skills
Job ID: 522829720
Originally Posted on: 5/29/2026