Senior SSD Controller Design Engineer

We are seeking a highly skilled Flash Controller Design Engineer to contribute to the design and development of next-generation NAND-based SSD controller solutions . The ideal candidate will have strong experience in pre-silicon ASIC/SoC design , controller architecture, RTL development, and design debug. This role requires end-to-end ownership of controller subsystems with a focus on performance, scalability, and reliability for enterprise and data-center storage products.

• Design and develop pre-silicon flash controller blocks and subsystems for NAND-based SSD controller products.
• Drive the complete design lifecycle including requirements analysis, architecture, micro-architecture, RTL implementation support, integration, debug, and design closure .
• Develop controller functionalities related to NAND flash management, data movement, performance optimization, and reliability enhancements .
• Perform design debugging, issue analysis, root-cause investigation, and problem resolution throughout the pre-silicon development cycle.
• Collaborate closely with architecture, verification, firmware, DFT, and post-silicon engineering teams to ensure successful feature delivery and product readiness.
• Support subsystem integration, interface definition, and design reviews across storage-controller SoC platforms.
• Contribute to scalable and robust controller solutions designed for enterprise and data-center SSD applications .

• Strong experience in pre-silicon design for flash controllers, storage controllers, ASIC, or SoC products .
• Hands-on expertise in flash controller architecture, design implementation, and design debug .
• Strong understanding of the complete end-to-end ASIC/SoC design lifecycle .
• Solid knowledge of NAND Flash technologies and associated protocols/interfaces .
• Experience with performance-sensitive, reliability-focused, and architecture-driven controller designs .
• Strong analytical, debugging, problem-solving, and cross-functional collaboration skills.